LineShine took first place on the TOP500 in June 2026. It runs HPL at 2.198 EFlop/s, 21.5% ahead of El Capitan, and there is no GPU anywhere in it. Every flop comes from an Armv9 CPU called LX2, 45,360 of them, each with a matrix engine inside every core. The National Supercomputing Center in Shenzhen (NSCS) runs it; the Shenzhen Cloud Computing Center built it.
The last Chinese number one was Sunway TaihuLight in 2017. China then stopped submitting, and the usual reading is that US export controls closed the door on high-end GPUs. LineShine is what you build when the accelerator is off the table: put the accelerator in the core.
NSCS calls the approach "online acceleration": scalar, vector and matrix work, communication and I/O all run in one CPU, one memory hierarchy and one software stack. Their own paper is careful to say it does not replace GPU machines for the largest dense AI training.
The machine on one page#
| HPL (Rmax) | 2,198.4 PFlop/s, 80.4% of peak |
| Peak FP64 (Rpeak) | 2,735.8 PFlop/s |
| HPCG | 22.00 PFlop/s, first in the world |
| HPL-MxP | 7.92 EFlop/s, fourth |
| Power during HPL | 42.22 MW, 52.07 GFlop/s per W |
| Nodes in the HPL run | 22,680, two LX2 each |
| Cores | 13,789,440 Armv9 cores at 1.55 GHz |
| Per socket | 304 cores, 32 GB HBM, 256 GB DDR, one 800 Gb/s NIC |
| Network | LingQi, dual-plane four-level fat tree, 1.6 Tb/s per node |
| Storage | about 200 PB, 10 TB/s fast tier |
| OS | Kylin Linux |
How these pages are organised#
Start with the chip, because everything else follows from it. The core page explains where the 128 flops per cycle come from. The memory page is the one to read if your code is a stencil or a sparse solver. The benchmark page compares LineShine with El Capitan, Frontier and Fugaku on more than HPL.
On the sources#
Almost everything public comes from five places: the TOP500 entry, an NSCS paper and press release, Jack Dongarra's report after his visit (ICL-UT-26-01), two arXiv papers by teams that ran on the full machine, and Glenn Lockwood's reconstruction from the ISC talk slides. Trade press fills the gaps. The sources disagree on a few points: node count, HBM capacity, the NIC layout. Each page flags those, and every number I derived myself is marked as such.