Skip to content
hpcnotes
Loading…
HPC·RAM & CPU Caches
2026.09.11· 1 min

Memory Bandwidth

Bytes per cycle from DRAM. If you are under the roof, it is not compute.
RAM & CPU Caches........................................................................................................................................................................................................Previous
Memory Latency........................................................................................................................................................................................................Next
#hpc
Memory Latency........................................................................................................................................................................................................2026.09.11
Cache Lines........................................................................................................................................................................................................2026.09.11
Memory Sharing........................................................................................................................................................................................................2026.09.11
Memory-Level Parallelism........................................................................................................................................................................................................2026.09.11
Prefetching........................................................................................................................................................................................................2026.09.11
Suggest an editMarkdownHistory